| Date | 10th, Jul 2019 |
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AMD has released the 7 nanometer 3900, 3950 and other Ryzen 3 processors. Samsung could be months from production of its 5-nanometer chips. This is all due to EUV (Extreme Ultraviolet) lithography finally getting solved. EUV lithography technology that we were waiting for 15 years for the semiconductor industry to solve. Extreme ultraviolet lithography is a next-generation lithography technology using a range of extreme ultraviolet (EUV) wavelengths, roughly spanning 13.4-13.7 nanometers.
It could be only 6 Years to the first 2 Nanometer chips. This surge of progress will also mean that China will not be able to catch up with US-South Korea and Taiwan Semiconductors for ten to fifteen years. China imports most of its semiconductor chips and China is restricted from buying the latest equipment from US sources. China was allowed to get some chip designs fabricated by Taiwan Semiconductor. Chinese companies are also restricted from hiring certain key technologists in lithography. Semiconductor Manufacturing International, China’s biggest chip manufacturer, is expected to have spent about $550m on R&D in 2018. The world semiconductor leaders (Taiwan Semiconductor, Intel and Samsung) all have research and capital spending that are up to ten times more than chinese chip companies.
There is a surge in computer performance from improved liquid cooling of high-performance systems. There is immersive liquid-cooled supercomputers and data centers with nearly exaflop performance in 2019 from DUG computing.
There are also improvements in specialized chip architectures. This will be a final surge in relatively conventional computing power.
The AMD Ryzen™ 9 3950X has 16 cores and up to 32 threads. It can hit a boost clock of 4.7 GHz.
Goatguy was pondering the release of the 7 nm AMD Ryzen “3” (3300, 3400, 3500, 3600, 3700, 3800, 3900 and 3950) processors, and it occurred to him, “well, that was quick”. Quick from the point of view that their newest TSMC 7 nm “rule” chips are hitting excellent compactness, excellent power-consumption, and excellent production yields, all within what, a year or two of the long-awaited introduction of EUV into conventional chip-manufacturing foundry lines? Something like that.
No sooner have these products — 4, 6, 8 … 12 and 16 core X86 processors, along with the “5700” high-billion transistor GPU — come forth, and here now we have another rather remarkable announcement:
Basically, it looks like Samsung as an early adopter will be able and well-invested to be producing 5 nm ARM-core processors (as well, we might surmise, as FAR more dense NVRAM-in-the-SSD-and-ThumbDrive format), aplenty. In 5 nm. Before the “ink” on the 7 hm UV process has dried!!!
Compared to 7nm, Samsung’s 5nm FinFET process technology provides up to a 25 percent increase in logic area efficiency with 20 percent lower power consumption or 10 percent higher performance as a result of process improvement to enable us to have more innovative standard cell architecture. The Samsung production line will cost $4.615 billion and will be completed in 2019 and will start high volume manufacturing in 2020.
Nextbigfuture reader Goatguy detects a kind of chip-making tsunami afoot. It was long considered a mature-to-the-point-of-diminishing-returns, the non-EUV processing that the whole chip industry was resigned to ‘deal with’ as the physics-bound end-point of sub-wavelength many-exposure nonlinear resist and advanced anisotropic molecular beam etching were able to achieve. What was needed, most-everyone agreed, was to be able to just use LIGHT of a far shorter wavelength, to do the patterning. From a process perspective, nothing could trump that.
But EUV (and now DUV for deep-ultraviolet, defined to be wavelengths smaller than 100 nm, but I suppose greater than the 20-or-lower nanometers of EUV) suffered from at least three technological complications.
[1] They couldn’t use lenses … because ALL glassy compounds at DUV and EUV wavelengths are essentially as opaque as jet-black glass.
[2] Using mirrors, even the (very necessary) coatings tended to absorb quite a bit of the EUV.
[3] Having to do all optics ‘’at a distance’’ in a vacuum, because AIR, or nitrogen, or helium would also refract, absorb and heat … causing aberrations in imaging.
The fourth was more of a stability issue: the smallest thermal variations would totally affect the placement of gates’ active elements (FET junctions) by many nanometers. So, thermal controls were quite finicky. Same could be said for microseismic vibrations in a plant. Every little jiggle becomes an error-in-imaging. VERY finicky. Not good for Silicon Valley, of course.
But, again, once those technology barriers were overcome, almost predictably we now see a wave, if not a harbor wave (translation of Tsunami from Japanese) of rapid advance in this area.
WHAT MIGHT BE EUV’s ENDPOINT? In a way analogous to the kind-of-endpoint of conventional lithography experienced at 14 nanometers, what might be expected from EUV and DUV? Moreover, how does DUV compliment EUV?
My 40-years-watching-the-industry (more like 50, but not wanting to sound too much like a fossil), I think there is very little standing in the way of year-to-2-year process cycles that dive deep into the lowest nanometer register, in the next 10 years. 7 —> 5 —> 4 —> 3 —> 2 nm, all seem quite possible. At some level, the ‘’problem’’ becomes that non-stoichiometric statistical placement of dopant (and lattice irregularities) atoms. Dopants, for those not well informed, are the necessary implanted atoms in an otherwise very, very, very well organized and pure substrate material, to ‘suck’ or ‘give’ additional electrons to the surrounding atoms, making the semiconductors so-implanted either more, or less conducting, and either more or less attractive to the flow of electrons, or their logical opposites, ‘’holes’’.
Whew. Don’t ask me to write that again!
But the bottom line is that in silicon, the atom-to-atom crystal lattice spacing is something like 0.27 nanometers or so. Which is to say, that in a semiconductor gate which is only perhaps 5 nm in scale length, there are only 18 atoms of silicon in that scale.
Talk about “atomic foundry rules”! That’s pretty dense. At 2.0 nm, we’re only talking about 7 atoms of width. Gee! That’s mind-bogglingly impressive.
Also, AMD has done something which I really didn’t foresee or expect: to deploy multiple ‘’chiplets’’ in their highest core-count processors. This is brilliant from a manufacturing perspective. Already AMD’s sort-of-fail chips (having 6 of 8 cores working) are sold as 6 core chips. Why not! Being able however to gang 2 of them up on a single for-sale substrate, along with a completely independent I/O-and-memory-bus chiplet … not using either 7 nm rules, or even the same manufacturing plants, but older plants, highly profitable in their golden years , well that’s just awesome. AMD gets to utilize a bunch of their not-quite-perfect chips to upsell the market on even higher core-count densities, “for free” so to speak.
My [Goatguys] OTHER prediction is that there is going to be a lot of activity in the next-generation of chip designers … of course just to utilize the 7-now-5 nanometer EUV for extant designs looking to increase performance by 50% OR MORE, and/or decrease chip size, and decrease power consumption … yah, sure them. But ALSO for brand-new designs of processors that aren’t just hugely parallel reduced-function nominally graphics-specialized such as GPUs, but in the very real, very tangible, next era of Artificial Intelligence, … chips that parallelize and radically change the computing requirements for inference engines. These too will be co-integrated onto the ‘’CPU’’ wafer board. All for $599.95 at your local Amazon pick-up-center.
Brian Wang is a Futurist Thought Leader and a popular Science blogger with 1 million readers per month. His blog Nextbigfuture.com is ranked #1 Science News Blog. It covers many disruptive technology and trends including Space, Robotics, Artificial Intelligence, Medicine, Anti-aging Biotechnology, and Nanotechnology.
Known for identifying cutting edge technologies, he is currently a Co-Founder of a startup and fundraiser for high potential early-stage companies. He is the Head of Research for Allocations for deep technology investments and an Angel Investor at Space Angels.
A frequent speaker at corporations, he has been a TEDx speaker, a Singularity University speaker and guest at numerous interviews for radio and podcasts. He is open to public speaking and advising engagements.
